diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..5f9a2f13d0da24e3adc96f90b8b0ce37513b9713 --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +template/* + +!template/Vivadofile +!template/*.xdc + diff --git a/README.md b/README.md index e04d52cf11ef55a70479d806f82ada0ecaf6b4ad..72b28786dd7990aa8de26fcd1e6c093c8d3cdae4 100644 --- a/README.md +++ b/README.md @@ -2,6 +2,20 @@ > Run vivado natively in linux command line. +## Features + +- Init, build, burn any vivado project in one command. + +- Extremely simple, flexible, and customizable project layout. + +- Burn auto saved built binary at anytime and any machine. + +- Full vivado GUI support. + +- Support every hardware supported by vivado. + +- Theoretically support any vivado version (But latest is the best). + ## Installation ```sh @@ -26,13 +40,11 @@ alias vivadow=vivado-wrapper # I'll use this wrapper in the doc below. mkdir my_project && cd my_project vivadow init code . # Or any editor you prefer. -vim Vivadofile # To tell vivado-wrapper about your module~constraint relationship. +vim Vivadofile # To tell vivado-wrapper about your module~constraint relationship, threads, board, etc. ``` - Build Project -Warning: this project will use `xc7a100tcsg324-1` (for HUST) as your board. Please fork and modify template if you'd like to use other board. We can easily support changing board by Vivadofile, if you can solve the TODO in ./vivado-wrapper:line5. - ```sh cd vivado-wrapper/example vivadow build diff --git a/gen_tcl.sh b/gen_tcl.sh index 1d36ef5c035111cd93bd8eb96eea93ff9f24c851..dcc29fc1ee44f08248cd7fa03a3eb507d1fbc25b 100755 --- a/gen_tcl.sh +++ b/gen_tcl.sh @@ -60,6 +60,18 @@ elif [[ $1 == gui ]]; then echo "open_project ${xpr} `find ${proj_dir}/*.srcs -regex '^.*\.s?vh?$' -exec echo add_files \{\} \;` start_gui" +elif [[ $1 == init-project ]]; then + proj_name="$2" + proj_dir="$3" + part_name="$4" # xc7a100tcsg324-1 + echo "# Generated by Vivado wrapper, licensed under GPL 3.0 + # Copyright (C) Recolic Keghart <root@recolic.net> + create_project ${proj_name} ${proj_dir} -part ${part_name} + file mkdir ${proj_dir}/${proj_name}.srcs/constrs_1/new + close [ open ${proj_dir}/${proj_name}.srcs/constrs_1/new/constraint.xdc w ] + add_files -fileset constrs_1 ${proj_dir}/${proj_name}.srcs/constrs_1/new/constraint.xdc" + rm -f ${proj_dir}/${proj_name}.srcs/constrs_1/new/constraint.xdc + rm -rf ${proj_dir}/${proj_name}.cache/* else echo "Usage: $0 build <xpr path> <run_name_synth> <run_name_impl> <to_step> <top module name> <threads_num> $0 burn <xpr path> <run_name_impl> <top_module_name> <dev_name(Ex:xc7a100t_0)>" diff --git a/template/Vivadofile b/template/Vivadofile index 599d22ef99b902f4e76558c170e0b65c95581540..b7d59a34e6bb9b9c1d97b47b6a50e4aaed37eaff 100644 --- a/template/Vivadofile +++ b/template/Vivadofile @@ -22,6 +22,9 @@ top_modules=( # top_module=test_main top_module= +# Name of your board in vivado. HUST uses 'xc7a100tcsg324-1' by default. +board="xc7a100tcsg324-1" + # # Optional options # diff --git a/template/project/temp_project.hw/temp_project.lpr b/template/project/temp_project.hw/temp_project.lpr deleted file mode 100644 index 0c1bafc6765c65115ba010b2684c9cfbb215adf9..0000000000000000000000000000000000000000 --- a/template/project/temp_project.hw/temp_project.lpr +++ /dev/null @@ -1,6 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!-- Product Version: Vivado v2018.1 (64-bit) --> -<!-- --> -<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --> - -<labtools version="1" minor="0"/> diff --git a/template/project/temp_project.srcs/constrs_1/new/constraint.xdc b/template/project/temp_project.srcs/constrs_1/new/constraint.xdc deleted file mode 100644 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000 diff --git a/template/project/temp_project.xpr b/template/project/temp_project.xpr deleted file mode 100644 index 751a429bbaf3db865cecdd97515e79865c10152b..0000000000000000000000000000000000000000 --- a/template/project/temp_project.xpr +++ /dev/null @@ -1,140 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!-- Product Version: Vivado v2018.1 (64-bit) --> -<!-- --> -<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --> - -<Project Version="7" Minor="36" Path="/home/recolic/tmp/_log/temp_project/temp_project.xpr"> - <DefaultLaunch Dir="$PRUNDIR"/> - <Configuration> - <Option Name="Id" Val="10aeba4a0c564ee4b9367894dc7cd541"/> - <Option Name="Part" Val="xc7a100tcsg324-1"/> - <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> - <Option Name="CompiledLibDirXSim" Val=""/> - <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> - <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> - <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/> - <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> - <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> - <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> - <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> - <Option Name="BoardPart" Val=""/> - <Option Name="ActiveSimSet" Val="sim_1"/> - <Option Name="DefaultLib" Val="xil_defaultlib"/> - <Option Name="ProjectType" Val="Default"/> - <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> - <Option Name="IPCachePermission" Val="read"/> - <Option Name="IPCachePermission" Val="write"/> - <Option Name="EnableCoreContainer" Val="FALSE"/> - <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> - <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> - <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> - <Option Name="EnableBDX" Val="FALSE"/> - <Option Name="DSAVendor" Val="xilinx"/> - <Option Name="DSANumComputeUnits" Val="60"/> - <Option Name="WTXSimLaunchSim" Val="0"/> - <Option Name="WTModelSimLaunchSim" Val="0"/> - <Option Name="WTQuestaLaunchSim" Val="0"/> - <Option Name="WTIesLaunchSim" Val="0"/> - <Option Name="WTVcsLaunchSim" Val="0"/> - <Option Name="WTRivieraLaunchSim" Val="0"/> - <Option Name="WTActivehdlLaunchSim" Val="0"/> - <Option Name="WTXSimExportSim" Val="0"/> - <Option Name="WTModelSimExportSim" Val="0"/> - <Option Name="WTQuestaExportSim" Val="0"/> - <Option Name="WTIesExportSim" Val="0"/> - <Option Name="WTVcsExportSim" Val="0"/> - <Option Name="WTRivieraExportSim" Val="0"/> - <Option Name="WTActivehdlExportSim" Val="0"/> - <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> - <Option Name="XSimRadix" Val="hex"/> - <Option Name="XSimTimeUnit" Val="ns"/> - <Option Name="XSimArrayDisplayLimit" Val="1024"/> - <Option Name="XSimTraceLimit" Val="65536"/> - <Option Name="SimTypes" Val="rtl"/> - </Configuration> - <FileSets Version="1" Minor="31"> - <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> - <Filter Type="Srcs"/> - <Config> - <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopAutoSet" Val="TRUE"/> - </Config> - </FileSet> - <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> - <Filter Type="Constrs"/> - <File Path="$PSRCDIR/constrs_1/new/constraint.xdc"> - <FileInfo> - <Attr Name="UsedIn" Val="synthesis"/> - <Attr Name="UsedIn" Val="implementation"/> - </FileInfo> - </File> - <Config> - <Option Name="ConstrsType" Val="XDC"/> - </Config> - </FileSet> - <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1"> - <Config> - <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopAutoSet" Val="TRUE"/> - <Option Name="TransportPathDelay" Val="0"/> - <Option Name="TransportIntDelay" Val="0"/> - <Option Name="SrcSet" Val="sources_1"/> - </Config> - </FileSet> - </FileSets> - <Simulators> - <Simulator Name="XSim"> - <Option Name="Description" Val="Vivado Simulator"/> - <Option Name="CompiledLib" Val="0"/> - </Simulator> - <Simulator Name="ModelSim"> - <Option Name="Description" Val="ModelSim Simulator"/> - </Simulator> - <Simulator Name="Questa"> - <Option Name="Description" Val="Questa Advanced Simulator"/> - </Simulator> - <Simulator Name="IES"> - <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/> - </Simulator> - <Simulator Name="Xcelium"> - <Option Name="Description" Val="Xcelium Parallel Simulator"/> - </Simulator> - <Simulator Name="VCS"> - <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/> - </Simulator> - <Simulator Name="Riviera"> - <Option Name="Description" Val="Riviera-PRO Simulator"/> - </Simulator> - </Simulators> - <Runs Version="1" Minor="10"> - <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true"> - <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"> - <Desc>Vivado Synthesis Defaults</Desc> - </StratHandle> - <Step Id="synth_design"/> - </Strategy> - <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/> - <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> - </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true"> - <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"> - <Desc>Default settings for Implementation.</Desc> - </StratHandle> - <Step Id="init_design"/> - <Step Id="opt_design"/> - <Step Id="power_opt_design"/> - <Step Id="place_design"/> - <Step Id="post_place_power_opt_design"/> - <Step Id="phys_opt_design"/> - <Step Id="route_design"/> - <Step Id="post_route_phys_opt_design"/> - <Step Id="write_bitstream"/> - </Strategy> - <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/> - <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> - </Run> - </Runs> - <Board/> -</Project> diff --git a/vivado-wrapper b/vivado-wrapper index 6ae897c068a600f207a66aaf848beac0af8f9596..fd99f405be7d0f1ac00d761e18be0b444002aeaa 100755 --- a/vivado-wrapper +++ b/vivado-wrapper @@ -1,11 +1,5 @@ #!/bin/bash -# TODO: Vivado create new project: -# create_project temp_project /home/recolic/tmp/_log/temp_project -part xc7a100tcsg324-1 -# file mkdir /home/recolic/tmp/_log/temp_project/temp_project.srcs/constrs_1/new -# close [ open /home/recolic/tmp/_log/temp_project/temp_project.srcs/constrs_1/new/constraint.xdc w ] -# add_files -fileset constrs_1 /home/recolic/tmp/_log/temp_project/temp_project.srcs/constrs_1/new/constraint.xdc - _vw_bin_name="$0" _vw_version_major="1" @@ -100,6 +94,7 @@ function import_vivadofile_impl () { [[ -e ./Vivadofile ]] && source ./Vivadofile && return 0 [[ -e ./vivadofile ]] && source ./vivadofile && return 0 [[ -e ./VivadoFile ]] && source ./VivadoFile && return 0 + [[ -e ./VIVADOFILE ]] && source ./VIVADOFILE && return 0 return 1 } @@ -129,37 +124,50 @@ function get_constraint_of_module () { kill -s TERM $_vw_mypid } +function vivado_check_and_init_template () { + [[ -z "$board" ]] && echo "You must set variable 'board'. Try \`vivadow init\` again." && return 4 + [[ -d "$my_path/template/$board" ]] && return 0 + "$my_path/gen_tcl.sh" init-project temp_project "$my_path/template/$board" "$board" > $temp_dir/sh.tcl + "$vivado_exec" -mode batch -source "$temp_dir/sh.tcl" -nojournal -nolog + rm -f "$my_path/template/$board/temp_project/temp_project.srcs/constrs_1/new/constraint.xdc" + rm -rf "$my_path/template/$board/temp_project.cache/"* +} + function generate_real_project () { [[ "$constr_path" == '' ]] && constr_path="$(pwd)/$(get_constraint_of_module $top_module)" - cp -r "$my_path/template/project" "$temp_dir/" + vivado_check_and_init_template || return 4 + cp -r "$my_path/template/"* "$temp_dir/" + ln -s "$temp_dir/$board" "$temp_dir/project" _real_proj_src="$temp_dir/project/temp_project.srcs" for src in `echo ${sources[@]}`; do mkdir -p "$_real_proj_src/sources_1/new/$(dirname "$src")" ln -s "$(pwd)/$src" "$_real_proj_src/sources_1/new/$src" done - rm "$_real_proj_src/constrs_1/new/constraint.xdc" + rm -f "$_real_proj_src/constrs_1/new/constraint.xdc" ln -s "$constr_path" "$_real_proj_src/constrs_1/new/constraint.xdc" echo "real_project generated at $temp_dir" } function clean_real_project () { - rm -rf $temp_dir + rm -rf $temp_dir ./.Xil echo "real_project cleaned" } function do_init () { mkdir constraint build src + [[ -f ./Vivadofile ]] && mv ./Vivadofile ./Vivadofile.backup cp "$my_path"/template/Vivadofile ./Vivadofile echo "init done." } function do_build () { generate_real_project + [[ $? -ne 0 ]] && echo "Generate real project failed." && clean_real_project && exit 4 "$my_path/gen_tcl.sh" build "$temp_dir/project/temp_project.xpr" synth_1 impl_1 write_bitstream "$top_module" $thread_num > $temp_dir/sh.tcl "$vivado_exec" -mode batch -source "$temp_dir/sh.tcl" -nojournal -nolog _bit_file="$temp_dir/project/temp_project.runs/impl_1/$top_module.bit" - [[ -e "$_bit_file" ]] && cp "$_bit_file" "$bit_dir/$top_module.bit" || echo "vivado-wrapper: Error: Build failed." + [[ -e "$_bit_file" ]] && cp "$_bit_file" "$bit_dir/$top_module.bit" || echo "vivado-wrapper: Error: Build failed. Please check previous error report." clean_real_project }