From 1a1d26bd0795131981cb25a6aa35c1cf82760892 Mon Sep 17 00:00:00 2001
From: Recolic Keghart <root@recolic.net>
Date: Mon, 3 Sep 2018 11:04:03 +0800
Subject: [PATCH] new board support done
---
gen_tcl.sh | 1 +
template/Vivadofile | 2 +-
.../temp_project.hw/temp_project.lpr | 6 +
.../constrs_1/new/constraint.xdc | 0
template/xc7a100tcsg324-1/temp_project.xpr | 139 ++++++++++++++++++
vivado-wrapper | 15 +-
6 files changed, 160 insertions(+), 3 deletions(-)
create mode 100644 template/xc7a100tcsg324-1/temp_project.hw/temp_project.lpr
create mode 100644 template/xc7a100tcsg324-1/temp_project.srcs/constrs_1/new/constraint.xdc
create mode 100644 template/xc7a100tcsg324-1/temp_project.xpr
diff --git a/gen_tcl.sh b/gen_tcl.sh
index fd8ce19..dcc29fc 100755
--- a/gen_tcl.sh
+++ b/gen_tcl.sh
@@ -71,6 +71,7 @@ elif [[ $1 == init-project ]]; then
close [ open ${proj_dir}/${proj_name}.srcs/constrs_1/new/constraint.xdc w ]
add_files -fileset constrs_1 ${proj_dir}/${proj_name}.srcs/constrs_1/new/constraint.xdc"
rm -f ${proj_dir}/${proj_name}.srcs/constrs_1/new/constraint.xdc
+ rm -rf ${proj_dir}/${proj_name}.cache/*
else
echo "Usage: $0 build <xpr path> <run_name_synth> <run_name_impl> <to_step> <top module name> <threads_num>
$0 burn <xpr path> <run_name_impl> <top_module_name> <dev_name(Ex:xc7a100t_0)>"
diff --git a/template/Vivadofile b/template/Vivadofile
index 8dae57e..b7d59a3 100644
--- a/template/Vivadofile
+++ b/template/Vivadofile
@@ -22,7 +22,7 @@ top_modules=(
# top_module=test_main
top_module=
-# Name of your board in vivado
+# Name of your board in vivado. HUST uses 'xc7a100tcsg324-1' by default.
board="xc7a100tcsg324-1"
#
diff --git a/template/xc7a100tcsg324-1/temp_project.hw/temp_project.lpr b/template/xc7a100tcsg324-1/temp_project.hw/temp_project.lpr
new file mode 100644
index 0000000..0c1bafc
--- /dev/null
+++ b/template/xc7a100tcsg324-1/temp_project.hw/temp_project.lpr
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
+
+<labtools version="1" minor="0"/>
diff --git a/template/xc7a100tcsg324-1/temp_project.srcs/constrs_1/new/constraint.xdc b/template/xc7a100tcsg324-1/temp_project.srcs/constrs_1/new/constraint.xdc
new file mode 100644
index 0000000..e69de29
diff --git a/template/xc7a100tcsg324-1/temp_project.xpr b/template/xc7a100tcsg324-1/temp_project.xpr
new file mode 100644
index 0000000..a06eeef
--- /dev/null
+++ b/template/xc7a100tcsg324-1/temp_project.xpr
@@ -0,0 +1,139 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.1 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
+
+<Project Version="7" Minor="36" Path="/home/recolic/code/vivado-wrapper/template/xc7a100tcsg324-1/temp_project.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="05e1233dc6b74ff8a9a27d141fdbb8d9"/>
+ <Option Name="Part" Val="xc7a100tcsg324-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="BoardPart" Val=""/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="DSAVendor" Val="xilinx"/>
+ <Option Name="DSANumComputeUnits" Val="60"/>
+ <Option Name="WTXSimLaunchSim" Val="0"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="0"/>
+ <Option Name="WTModelSimExportSim" Val="0"/>
+ <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="0"/>
+ <Option Name="WTRivieraExportSim" Val="0"/>
+ <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ </Configuration>
+ <FileSets Version="1" Minor="31">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PSRCDIR/constrs_1/new/constraint.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="IES">
+ <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="10">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ </Run>
+ </Runs>
+ <Board/>
+</Project>
diff --git a/vivado-wrapper b/vivado-wrapper
index e4f948e..82acc4b 100755
--- a/vivado-wrapper
+++ b/vivado-wrapper
@@ -129,10 +129,20 @@ function get_constraint_of_module () {
kill -s TERM $_vw_mypid
}
+function vivado_check_and_init_template () {
+ [[ -e "$board" ]] && echo "You must set variable 'board'. Try \`vivadow init\` again."
+ [[ -d "$my_path/template/$board" ]] && return 0
+ "$my_path/gen_tcl.sh" init-project temp_project "$my_path/template/$board" "$board" > $temp_dir/sh.tcl
+ "$vivado_exec" -mode batch -source "$temp_dir/sh.tcl" -nojournal -nolog
+ rm -f "$my_path/template/$board/temp_project/temp_project.srcs/constrs_1/new/constraint.xdc"
+ rm -rf "$my_path/template/$board/temp_project.cache/"*
+}
+
function generate_real_project () {
[[ "$constr_path" == '' ]] && constr_path="$(pwd)/$(get_constraint_of_module $top_module)"
- cp -r "$my_path/template/project" "$temp_dir/"
- # todo: use new init-project to generate if template not exist
+ vivado_check_and_init_template
+ cp -r "$my_path/template/"* "$temp_dir/"
+ ln -s "$temp_dir/$board" "$temp_dir/project"
_real_proj_src="$temp_dir/project/temp_project.srcs"
for src in `echo ${sources[@]}`; do
mkdir -p "$_real_proj_src/sources_1/new/$(dirname "$src")"
@@ -150,6 +160,7 @@ function clean_real_project () {
function do_init () {
mkdir constraint build src
+ [[ -f ./Vivadofile ]] && mv ./Vivadofile ./Vivadofile.backup
cp "$my_path"/template/Vivadofile ./Vivadofile
echo "init done."
}
--
GitLab