From c0a625513227e9b45b9e39c314662d303ed7646a Mon Sep 17 00:00:00 2001 From: Recolic Keghart <root@recolic.net> Date: Mon, 3 Sep 2018 11:25:38 +0800 Subject: [PATCH] Bug fix and error deal improvement on gen_real_proj --- .../project/temp_project.hw/temp_project.lpr | 6 - .../constrs_1/new/constraint.xdc | 0 template/project/temp_project.xpr | 140 ------------------ .../temp_project.hw/temp_project.lpr | 6 - .../constrs_1/new/constraint.xdc | 0 template/xc7a100tcsg324-1/temp_project.xpr | 139 ----------------- vivado-wrapper | 8 +- 7 files changed, 5 insertions(+), 294 deletions(-) delete mode 100644 template/project/temp_project.hw/temp_project.lpr delete mode 100644 template/project/temp_project.srcs/constrs_1/new/constraint.xdc delete mode 100644 template/project/temp_project.xpr delete mode 100644 template/xc7a100tcsg324-1/temp_project.hw/temp_project.lpr delete mode 100644 template/xc7a100tcsg324-1/temp_project.srcs/constrs_1/new/constraint.xdc delete mode 100644 template/xc7a100tcsg324-1/temp_project.xpr diff --git a/template/project/temp_project.hw/temp_project.lpr b/template/project/temp_project.hw/temp_project.lpr deleted file mode 100644 index 0c1bafc..0000000 --- a/template/project/temp_project.hw/temp_project.lpr +++ /dev/null @@ -1,6 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!-- Product Version: Vivado v2018.1 (64-bit) --> -<!-- --> -<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --> - -<labtools version="1" minor="0"/> diff --git a/template/project/temp_project.srcs/constrs_1/new/constraint.xdc b/template/project/temp_project.srcs/constrs_1/new/constraint.xdc deleted file mode 100644 index e69de29..0000000 diff --git a/template/project/temp_project.xpr b/template/project/temp_project.xpr deleted file mode 100644 index 751a429..0000000 --- a/template/project/temp_project.xpr +++ /dev/null @@ -1,140 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!-- Product Version: Vivado v2018.1 (64-bit) --> -<!-- --> -<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --> - -<Project Version="7" Minor="36" Path="/home/recolic/tmp/_log/temp_project/temp_project.xpr"> - <DefaultLaunch Dir="$PRUNDIR"/> - <Configuration> - <Option Name="Id" Val="10aeba4a0c564ee4b9367894dc7cd541"/> - <Option Name="Part" Val="xc7a100tcsg324-1"/> - <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> - <Option Name="CompiledLibDirXSim" Val=""/> - <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> - <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> - <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/> - <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> - <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> - <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> - <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> - <Option Name="BoardPart" Val=""/> - <Option Name="ActiveSimSet" Val="sim_1"/> - <Option Name="DefaultLib" Val="xil_defaultlib"/> - <Option Name="ProjectType" Val="Default"/> - <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> - <Option Name="IPCachePermission" Val="read"/> - <Option Name="IPCachePermission" Val="write"/> - <Option Name="EnableCoreContainer" Val="FALSE"/> - <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> - <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> - <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> - <Option Name="EnableBDX" Val="FALSE"/> - <Option Name="DSAVendor" Val="xilinx"/> - <Option Name="DSANumComputeUnits" Val="60"/> - <Option Name="WTXSimLaunchSim" Val="0"/> - <Option Name="WTModelSimLaunchSim" Val="0"/> - <Option Name="WTQuestaLaunchSim" Val="0"/> - <Option Name="WTIesLaunchSim" Val="0"/> - <Option Name="WTVcsLaunchSim" Val="0"/> - <Option Name="WTRivieraLaunchSim" Val="0"/> - <Option Name="WTActivehdlLaunchSim" Val="0"/> - <Option Name="WTXSimExportSim" Val="0"/> - <Option Name="WTModelSimExportSim" Val="0"/> - <Option Name="WTQuestaExportSim" Val="0"/> - <Option Name="WTIesExportSim" Val="0"/> - <Option Name="WTVcsExportSim" Val="0"/> - <Option Name="WTRivieraExportSim" Val="0"/> - <Option Name="WTActivehdlExportSim" Val="0"/> - <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> - <Option Name="XSimRadix" Val="hex"/> - <Option Name="XSimTimeUnit" Val="ns"/> - <Option Name="XSimArrayDisplayLimit" Val="1024"/> - <Option Name="XSimTraceLimit" Val="65536"/> - <Option Name="SimTypes" Val="rtl"/> - </Configuration> - <FileSets Version="1" Minor="31"> - <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> - <Filter Type="Srcs"/> - <Config> - <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopAutoSet" Val="TRUE"/> - </Config> - </FileSet> - <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> - <Filter Type="Constrs"/> - <File Path="$PSRCDIR/constrs_1/new/constraint.xdc"> - <FileInfo> - <Attr Name="UsedIn" Val="synthesis"/> - <Attr Name="UsedIn" Val="implementation"/> - </FileInfo> - </File> - <Config> - <Option Name="ConstrsType" Val="XDC"/> - </Config> - </FileSet> - <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1"> - <Config> - <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopAutoSet" Val="TRUE"/> - <Option Name="TransportPathDelay" Val="0"/> - <Option Name="TransportIntDelay" Val="0"/> - <Option Name="SrcSet" Val="sources_1"/> - </Config> - </FileSet> - </FileSets> - <Simulators> - <Simulator Name="XSim"> - <Option Name="Description" Val="Vivado Simulator"/> - <Option Name="CompiledLib" Val="0"/> - </Simulator> - <Simulator Name="ModelSim"> - <Option Name="Description" Val="ModelSim Simulator"/> - </Simulator> - <Simulator Name="Questa"> - <Option Name="Description" Val="Questa Advanced Simulator"/> - </Simulator> - <Simulator Name="IES"> - <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/> - </Simulator> - <Simulator Name="Xcelium"> - <Option Name="Description" Val="Xcelium Parallel Simulator"/> - </Simulator> - <Simulator Name="VCS"> - <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/> - </Simulator> - <Simulator Name="Riviera"> - <Option Name="Description" Val="Riviera-PRO Simulator"/> - </Simulator> - </Simulators> - <Runs Version="1" Minor="10"> - <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true"> - <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"> - <Desc>Vivado Synthesis Defaults</Desc> - </StratHandle> - <Step Id="synth_design"/> - </Strategy> - <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/> - <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> - </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true"> - <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"> - <Desc>Default settings for Implementation.</Desc> - </StratHandle> - <Step Id="init_design"/> - <Step Id="opt_design"/> - <Step Id="power_opt_design"/> - <Step Id="place_design"/> - <Step Id="post_place_power_opt_design"/> - <Step Id="phys_opt_design"/> - <Step Id="route_design"/> - <Step Id="post_route_phys_opt_design"/> - <Step Id="write_bitstream"/> - </Strategy> - <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/> - <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> - </Run> - </Runs> - <Board/> -</Project> diff --git a/template/xc7a100tcsg324-1/temp_project.hw/temp_project.lpr b/template/xc7a100tcsg324-1/temp_project.hw/temp_project.lpr deleted file mode 100644 index 0c1bafc..0000000 --- a/template/xc7a100tcsg324-1/temp_project.hw/temp_project.lpr +++ /dev/null @@ -1,6 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!-- Product Version: Vivado v2018.1 (64-bit) --> -<!-- --> -<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --> - -<labtools version="1" minor="0"/> diff --git a/template/xc7a100tcsg324-1/temp_project.srcs/constrs_1/new/constraint.xdc b/template/xc7a100tcsg324-1/temp_project.srcs/constrs_1/new/constraint.xdc deleted file mode 100644 index e69de29..0000000 diff --git a/template/xc7a100tcsg324-1/temp_project.xpr b/template/xc7a100tcsg324-1/temp_project.xpr deleted file mode 100644 index a06eeef..0000000 --- a/template/xc7a100tcsg324-1/temp_project.xpr +++ /dev/null @@ -1,139 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!-- Product Version: Vivado v2018.1 (64-bit) --> -<!-- --> -<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --> - -<Project Version="7" Minor="36" Path="/home/recolic/code/vivado-wrapper/template/xc7a100tcsg324-1/temp_project.xpr"> - <DefaultLaunch Dir="$PRUNDIR"/> - <Configuration> - <Option Name="Id" Val="05e1233dc6b74ff8a9a27d141fdbb8d9"/> - <Option Name="Part" Val="xc7a100tcsg324-1"/> - <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> - <Option Name="CompiledLibDirXSim" Val=""/> - <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> - <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> - <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/> - <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> - <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> - <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> - <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> - <Option Name="BoardPart" Val=""/> - <Option Name="ActiveSimSet" Val="sim_1"/> - <Option Name="DefaultLib" Val="xil_defaultlib"/> - <Option Name="ProjectType" Val="Default"/> - <Option Name="IPCachePermission" Val="read"/> - <Option Name="IPCachePermission" Val="write"/> - <Option Name="EnableCoreContainer" Val="FALSE"/> - <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> - <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> - <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> - <Option Name="EnableBDX" Val="FALSE"/> - <Option Name="DSAVendor" Val="xilinx"/> - <Option Name="DSANumComputeUnits" Val="60"/> - <Option Name="WTXSimLaunchSim" Val="0"/> - <Option Name="WTModelSimLaunchSim" Val="0"/> - <Option Name="WTQuestaLaunchSim" Val="0"/> - <Option Name="WTIesLaunchSim" Val="0"/> - <Option Name="WTVcsLaunchSim" Val="0"/> - <Option Name="WTRivieraLaunchSim" Val="0"/> - <Option Name="WTActivehdlLaunchSim" Val="0"/> - <Option Name="WTXSimExportSim" Val="0"/> - <Option Name="WTModelSimExportSim" Val="0"/> - <Option Name="WTQuestaExportSim" Val="0"/> - <Option Name="WTIesExportSim" Val="0"/> - <Option Name="WTVcsExportSim" Val="0"/> - <Option Name="WTRivieraExportSim" Val="0"/> - <Option Name="WTActivehdlExportSim" Val="0"/> - <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> - <Option Name="XSimRadix" Val="hex"/> - <Option Name="XSimTimeUnit" Val="ns"/> - <Option Name="XSimArrayDisplayLimit" Val="1024"/> - <Option Name="XSimTraceLimit" Val="65536"/> - <Option Name="SimTypes" Val="rtl"/> - </Configuration> - <FileSets Version="1" Minor="31"> - <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> - <Filter Type="Srcs"/> - <Config> - <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopAutoSet" Val="TRUE"/> - </Config> - </FileSet> - <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> - <Filter Type="Constrs"/> - <File Path="$PSRCDIR/constrs_1/new/constraint.xdc"> - <FileInfo> - <Attr Name="UsedIn" Val="synthesis"/> - <Attr Name="UsedIn" Val="implementation"/> - </FileInfo> - </File> - <Config> - <Option Name="ConstrsType" Val="XDC"/> - </Config> - </FileSet> - <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1"> - <Config> - <Option Name="DesignMode" Val="RTL"/> - <Option Name="TopAutoSet" Val="TRUE"/> - <Option Name="TransportPathDelay" Val="0"/> - <Option Name="TransportIntDelay" Val="0"/> - <Option Name="SrcSet" Val="sources_1"/> - </Config> - </FileSet> - </FileSets> - <Simulators> - <Simulator Name="XSim"> - <Option Name="Description" Val="Vivado Simulator"/> - <Option Name="CompiledLib" Val="0"/> - </Simulator> - <Simulator Name="ModelSim"> - <Option Name="Description" Val="ModelSim Simulator"/> - </Simulator> - <Simulator Name="Questa"> - <Option Name="Description" Val="Questa Advanced Simulator"/> - </Simulator> - <Simulator Name="IES"> - <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/> - </Simulator> - <Simulator Name="Xcelium"> - <Option Name="Description" Val="Xcelium Parallel Simulator"/> - </Simulator> - <Simulator Name="VCS"> - <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/> - </Simulator> - <Simulator Name="Riviera"> - <Option Name="Description" Val="Riviera-PRO Simulator"/> - </Simulator> - </Simulators> - <Runs Version="1" Minor="10"> - <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true"> - <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"> - <Desc>Vivado Synthesis Defaults</Desc> - </StratHandle> - <Step Id="synth_design"/> - </Strategy> - <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/> - <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> - </Run> - <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true"> - <Strategy Version="1" Minor="2"> - <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"> - <Desc>Default settings for Implementation.</Desc> - </StratHandle> - <Step Id="init_design"/> - <Step Id="opt_design"/> - <Step Id="power_opt_design"/> - <Step Id="place_design"/> - <Step Id="post_place_power_opt_design"/> - <Step Id="phys_opt_design"/> - <Step Id="route_design"/> - <Step Id="post_route_phys_opt_design"/> - <Step Id="write_bitstream"/> - </Strategy> - <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/> - <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> - </Run> - </Runs> - <Board/> -</Project> diff --git a/vivado-wrapper b/vivado-wrapper index 82acc4b..8bca6bf 100755 --- a/vivado-wrapper +++ b/vivado-wrapper @@ -100,6 +100,7 @@ function import_vivadofile_impl () { [[ -e ./Vivadofile ]] && source ./Vivadofile && return 0 [[ -e ./vivadofile ]] && source ./vivadofile && return 0 [[ -e ./VivadoFile ]] && source ./VivadoFile && return 0 + [[ -e ./VIVADOFILE ]] && source ./VIVADOFILE && return 0 return 1 } @@ -130,7 +131,7 @@ function get_constraint_of_module () { } function vivado_check_and_init_template () { - [[ -e "$board" ]] && echo "You must set variable 'board'. Try \`vivadow init\` again." + [[ -z "$board" ]] && echo "You must set variable 'board'. Try \`vivadow init\` again." && return 4 [[ -d "$my_path/template/$board" ]] && return 0 "$my_path/gen_tcl.sh" init-project temp_project "$my_path/template/$board" "$board" > $temp_dir/sh.tcl "$vivado_exec" -mode batch -source "$temp_dir/sh.tcl" -nojournal -nolog @@ -140,7 +141,7 @@ function vivado_check_and_init_template () { function generate_real_project () { [[ "$constr_path" == '' ]] && constr_path="$(pwd)/$(get_constraint_of_module $top_module)" - vivado_check_and_init_template + vivado_check_and_init_template || return 4 cp -r "$my_path/template/"* "$temp_dir/" ln -s "$temp_dir/$board" "$temp_dir/project" _real_proj_src="$temp_dir/project/temp_project.srcs" @@ -167,11 +168,12 @@ function do_init () { function do_build () { generate_real_project + [[ $? -ne 0 ]] && echo "Generate real project failed." && clean_real_project && exit 4 "$my_path/gen_tcl.sh" build "$temp_dir/project/temp_project.xpr" synth_1 impl_1 write_bitstream "$top_module" $thread_num > $temp_dir/sh.tcl "$vivado_exec" -mode batch -source "$temp_dir/sh.tcl" -nojournal -nolog _bit_file="$temp_dir/project/temp_project.runs/impl_1/$top_module.bit" - [[ -e "$_bit_file" ]] && cp "$_bit_file" "$bit_dir/$top_module.bit" || echo "vivado-wrapper: Error: Build failed." + [[ -e "$_bit_file" ]] && cp "$_bit_file" "$bit_dir/$top_module.bit" || echo "vivado-wrapper: Error: Build failed. Please check previous error report." clean_real_project } -- GitLab