diff --git a/template/Vivadofile b/template/Vivadofile
index e200fb1036fde019b76edb160fc7e8ec637576ac..599d22ef99b902f4e76558c170e0b65c95581540 100644
--- a/template/Vivadofile
+++ b/template/Vivadofile
@@ -4,7 +4,7 @@
 
 # You may use SystemVerilog, Verilog, or VHDL files as sources.
 # sources=(test_main.sv lib/* ./mod?.v)
-sources=()
+sources=(src/*)
 
 # The directory where generated bitstream is put
 bit_dir=./build
diff --git a/vivado-wrapper b/vivado-wrapper
index 626cf9338f89b4aeea5cc743475e99eb2e71af40..9f723658ce9f1b20ff1925d69066fb76f0e5f9d0 100755
--- a/vivado-wrapper
+++ b/vivado-wrapper
@@ -139,7 +139,7 @@ function clean_real_project () {
 }
 
 function do_init () {
-    mkdir constraint build
+    mkdir constraint build src
     cp "$my_path"/template/Vivadofile ./Vivadofile
     echo "init done."
 }