diff --git a/nemu/include/cpu/reg.h b/nemu/include/cpu/reg.h
index 469a8d5b67cae540f17197b53a5b2aca223a672b..bcfa3f9d72c5c6f61ef54ecd0d9acf3a64d8a3c1 100644
--- a/nemu/include/cpu/reg.h
+++ b/nemu/include/cpu/reg.h
@@ -14,21 +14,22 @@ enum { R_AL, R_CL, R_DL, R_BL, R_AH, R_CH, R_DH, R_BH };
  * For more details about the register encoding scheme, see i386 manual.
  */
 
-typedef struct {
-  struct {
+typedef union {
+  union {
     uint32_t _32;
     uint16_t _16;
     uint8_t _8[2];
-  } gpr[8];
+  } gpr[9];
 
   /* Do NOT change the order of the GPRs' definitions. */
 
   /* In NEMU, rtlreg_t is exactly uint32_t. This makes RTL instructions
    * in PA2 able to directly access these registers.
    */
-  rtlreg_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
-
-  vaddr_t eip;
+  struct {
+    rtlreg_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
+    vaddr_t eip;
+  };
 
 } CPU_state;
 
@@ -57,4 +58,5 @@ static inline const char* reg_name(int index, int width) {
   }
 }
 
+
 #endif
diff --git a/nemu/src/cpu/reg.c b/nemu/src/cpu/reg.c
index 2f85402abe114b5a38f767e391dbbbd76552ade3..2eba473a5cdbe7b231f0631e249ad9981cfe1f4a 100644
--- a/nemu/src/cpu/reg.c
+++ b/nemu/src/cpu/reg.c
@@ -8,7 +8,15 @@ const char *regsl[] = {"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"};
 const char *regsw[] = {"ax", "cx", "dx", "bx", "sp", "bp", "si", "di"};
 const char *regsb[] = {"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"};
 
+inline void rcpu_bootstrap_check_1() {
+  assert(sizeof(rtlreg_t) == sizeof(uint32_t));
+  assert(sizeof(vaddr_t) == sizeof(uint32_t));
+  printf("Recolic bootstrap test %s passed.\n", __FILE__);
+}
+
 void reg_test() {
+  rcpu_bootstrap_check_1();
+
   srand(time(0));
   uint32_t sample[8];
   uint32_t eip_sample = rand();