- Mar 21, 2018
- Mar 20, 2018
- Mar 19, 2018
-
-
Subv authored
-
Subv authored
-
bunnei authored
Implement Pull #3064 from citra: Clean all format warnings (Yuzu-specific format warnings cleared too)
-
N00byKing authored
-
N00byKing authored
-
N00byKing authored
-
N00byKing authored
-
bunnei authored
GPU: Added TIC and TSC registers to the Maxwell3D register structure.
-
Subv authored
-
Subv authored
-
bunnei authored
Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
-
bunnei authored
vi: TransactParcel DequeueBuffer should wait current thread
-
bunnei authored
GPU: Implement macro 0xE1A BindTextureInfoBuffer in HLE.
-
bunnei authored
-
bunnei authored
-
bunnei authored
-
bunnei authored
-
bunnei authored
-
Subv authored
This macro simply sets the current CB_ADDRESS to the texture buffer address for the input shader stage.
-
- Mar 18, 2018