Skip to content
Snippets Groups Projects
Unverified Commit 03a979a6 authored by Recolic Keghart's avatar Recolic Keghart
Browse files

main function implemented. optional cmdline args not implemented. No testing is done.

parent 6a2d9d7e
No related branches found
No related tags found
No related merge requests found
Hide whitespace changes
Inline Side-by-side
Showing
with 285 additions and 34 deletions
README.md 0 → 100644
+ 6
− 0
View file @ 03a979a6
##
Warning: this project will use xc7a100tcsg324-1 (HUST) as your board. Please fork and modify template if you'd like to use other board.
Warning: this script maybe injected, so DO NOT trust Vivadofile uploaded by others!!!
burn_file.sh deleted 100755 → 0
+ 0
− 6
View file @ 6a2d9d7e
#!/bin/bash
_tmp=`mktemp`
vivado_exec="/home/recolic/extraDisk/xilinx/Vivado/2018.1/bin/vivado"
`dirname $0`/gen_tcl.sh burn-file $1 > $_tmp
$vivado_exec -mode batch -source $_tmp
rm -f $_tmp
example/Vivadofile
+ 2
− 2
View file @ 03a979a6
......@@ -7,7 +7,7 @@ sources=(test_main.sv lib/* ./mod?.v)
bit_dir=./build
top_modules=(
"test_main:constrain/test_main.xdc"
"mod1:constrain/mod1.xdc"
"test_main:constraint/test_main.xdc"
"mod1:constraint/mod1.xdc"
)
top_module=test_main
\ No newline at end of file
example/constrain/mod1.xdc → example/constraint/mod1.xdc
+ 0
− 0
View file @ 03a979a6
File moved
example/constrain/test_main.xdc → example/constraint/test_main.xdc
+ 0
− 0
View file @ 03a979a6
File moved
main.sh 100644 → 100755
+ 93
− 5
View file @ 03a979a6
......@@ -3,7 +3,7 @@
_vw_bin_name="$0"
_vw_version_major="0"
_vw_version_minor="1"
_vw_version_minor="2"
_vw_version="${_vw_version_major}.${_vw_version_minor}"
[[ $_vw_version_major == 0 ]] && echo "Vivado wrapper is unfinished, and unable to work." && exit 11
......@@ -27,8 +27,8 @@ SubCommands:
Build current project, using ./Vivadofile as configuration file.
--top <top_module_name>
Override top module appointed in Vivadofile.
--constrain <path/to/constrain.xdc>
Override the constrain file appointed in Vivadofile.
--constraint <path/to/constraint.xdc>
Override the constraint file appointed in Vivadofile.
burn (Vivadofile required)
Burn compiled top_module bit file into hardware board.
......@@ -56,6 +56,22 @@ Examples:
"
}
function where_is_him () {
SOURCE="$1"
while [ -h "$SOURCE" ]; do # resolve $SOURCE until the file is no longer a symlink
DIR="$( cd -P "$( dirname "$SOURCE" )" && pwd )"
SOURCE="$(readlink "$SOURCE")"
[[ $SOURCE != /* ]] && SOURCE="$DIR/$SOURCE" # if $SOURCE was a relative symlink, we need to resolve it relative to the path where the symlink file was located
done
DIR="$( cd -P "$( dirname "$SOURCE" )" && pwd )"
echo -n "$DIR"
}
function where_am_i () {
_my_path=`type -p ${_vw_bin_name}`
where_is_him "$_my_path"
}
function import_vivadofile_impl () {
[[ -e ./Vivadofile ]] && source ./Vivadofile && return 0
[[ -e ./vivadofile ]] && source ./vivadofile && return 0
......@@ -75,7 +91,7 @@ function import_vivadofile () {
[[ "${top_module}" == '' ]] && echo "top_module not provided." && return 1
}
function get_constrain_of_module () {
function get_constraint_of_module () {
_mod_name="$1"
for _ele in "${top_modules[@]}" ; do
_key=${_ele%%:*}
......@@ -85,7 +101,59 @@ function get_constrain_of_module () {
return 1
}
vw_cmd="$1"
function generate_real_project () {
# Create a temp real vivado project in /tmp, link all sources to it, and prepare for future usage.
cp -r "$my_path/template/project" "$temp_dir/"
for src in `echo ${sources[@]}`; do
_unpathed_src=`echo $src | tr '/' '_' | tr ' ' '_'`
ln -s "$(pwd)/$src" "$temp_dir/project/temp-project.srcs/sources_1/new/$_unpathed_src"
done
rm "$temp_dir/project/temp-project.srcs/constrs_1/new/constraint.xdc"
ln -s "$constr_path" "$temp_dir/project/temp-project.srcs/constrs_1/new/constraint.xdc"
echo "real_project generated at $temp_dir"
}
function clean_real_project () {
rm -rf $temp_dir
echo "real_project cleaned"
}
function do_init () {
mkdir constraint build
cp "$my_path"/template/Vivadofile ./Vivadofile
echo "init done."
}
function do_build () {
# TODO: Parse cmdline, override top_module and constr
constr_path="$(pwd)/$(get_constraint_of_module $top_module)"
generate_real_project
"$my_path/gen_tcl.sh" build "$temp_dir/project/temp-project.xpr" synth_1 impl_1 write_bitstream "$top_module" $thread_num > $temp_dir/sh.tcl
"$vivado_exec" -mode batch -source "$temp_dir/sh.tcl" -nojournal -nolog
_bit_file="$temp_dir/project/temp-project.runs/impl_1/$top_module.bit"
[[ -e "$_bit_file" ]] && cp "$_bit_file" "$bit_dir/$top_module.bit" || echo "vivado-wrapper: Error: Build failed."
clean_real_project
}
function burn_file () {
# TODO: Parse cmdline to get device_name if any.
file_to_burn="$1"
"$my_path/gen_tcl.sh" burn-file "$file_to_burn" > $temp_dir/sh.tcl
"$vivado_exec" -mode batch -source "$temp_dir/sh.tcl" -nojournal -nolog
}
function do_burn () {
# TODO: Parse cmdline, override top_module and device_name
burn_file "$bit_dir/$top_module.bit"
}
my_path=`where_am_i`
temp_dir=`mktemp -d`
# If noob user add space character in $1, just truncate it.
vw_cmd=$1
shift
[[ $vw_cmd == '' ]] && show_help && exit 1
[[ $vw_cmd == '--help' ]] && show_help && exit 0
......@@ -94,4 +162,24 @@ if [[ $vw_cmd == 'build' ]] || [[ $vw_cmd == 'burn' ]] || [[ $vw_cmd == 'gui' ]]
[[ $? != 0 ]] && echo "Vivadofile error reported. Exiting..." && exit 2
fi
case $vw_cmd in
'init' )
do_init
;;
'build' )
do_build
;;
'burn' )
do_burn
;;
'gui' )
do_gui &
;;
'burn-file' )
burn_file $1
;;
* )
echo "Unknown command '${vw_cmd}', try '${_vw_bin_name} --help'"
;;
esac
template/Vivadofile 0 → 100644
+ 33
− 0
View file @ 03a979a6
#
# Required options
#
# You may use SystemVerilog, Verilog, or VHDL files as sources.
# sources=(test_main.sv lib/* ./mod?.v)
sources=()
# The directory where generated bitstream is put
bit_dir=./build
# All of your top_modules and its constraint files.
# top_modules=(
# "test_main:constraint/test_main.xdc"
# "mod1:constraint/mod1.xdc"
# )
top_modules=(
)
# Your default top_module. Maybe override by commandline option.
# top_module=test_main
top_module=
#
# Optional options
#
# Path to vivado executable. It will override environment variable `vivado_exec`
# vivado_exec="/path/to/vivado"
# It's recommanded to set thread_num to cores of your CPU.
# thread_num=4
template/project/temp-project.hw/temp-project.lpr 0 → 100644
+ 6
− 0
View file @ 03a979a6
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
template/project/temp-project.xpr 0 → 100644
+ 145
− 0
View file @ 03a979a6
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="36" Path="/home/recolic/tmp/temp-project/temp-project.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="f82f6a5f20b647dc83d6a988b89187d3"/>
<Option Name="Part" Val="xc7a100tcsg324-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/test.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/constraint.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<Board/>
</Project>
vivado.mk deleted 100644 → 0
+ 0
− 21
View file @ 6a2d9d7e
vivado_exec = /home/recolic/extraDisk/xilinx/Vivado/2018.1/bin/vivado
_tmp := $(shell mktemp)
build: clean
./gen_tcl.sh build $(xpr_path) synth_1 impl_1 write_bitstream $(top_module) 4 > $(_tmp)
$(vivado_exec) -mode batch -source $(_tmp)
rm -f $(_tmp)
burn: clean
./gen_tcl.sh burn $(xpr_path) impl_1 $(top_module) > $(_tmp)
$(vivado_exec) -mode batch -source $(_tmp)
rm -f $(_tmp)
gui: clean
./gen_tcl.sh gui $(xpr_path) > $(_tmp)
$(vivado_exec) -mode batch -source $(_tmp)
rm -f $(_tmp)
clean:
rm -f *.jou *.log *.str
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment