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Unverified Commit 7bce3f67 authored by Recolic Keghart's avatar Recolic Keghart
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clean up junks

parent 3bd4d6d3
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#
# Required options
#
# You may use SystemVerilog, Verilog, or VHDL files as sources.
# sources=(test_main.sv lib/* ./mod?.v)
sources=()
# The directory where generated bitstream is put
bit_dir=./build
# All of your top_modules and its constraint files.
# top_modules=(
# "test_main:constraint/test_main.xdc"
# "mod1:constraint/mod1.xdc"
# )
top_modules=(
)
# Your default top_module. Maybe override by commandline option.
# top_module=test_main
top_module=
#
# Optional options
#
# Path to vivado executable. It will override environment variable `vivado_exec`
# vivado_exec="/path/to/vivado"
# It's recommanded to set thread_num to cores of your CPU.
# thread_num=4
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