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Unverified Commit c7e52288 authored by Recolic Keghart's avatar Recolic Keghart
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init src folder

parent 064c70dd
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......@@ -4,7 +4,7 @@
# You may use SystemVerilog, Verilog, or VHDL files as sources.
# sources=(test_main.sv lib/* ./mod?.v)
sources=()
sources=(src/*)
# The directory where generated bitstream is put
bit_dir=./build
......
......@@ -139,7 +139,7 @@ function clean_real_project () {
}
function do_init () {
mkdir constraint build
mkdir constraint build src
cp "$my_path"/template/Vivadofile ./Vivadofile
echo "init done."
}
......
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